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1 ?2004 integrated device technology, inc. june 2004 dsc-2692/16 high speed 2k x 8 dual port static ram idt7132sa/la idt7142sa/la functional block diagram features high-speed access ? commercial: 20/25/35/55/100ns (max.) ? industrial: 25ns (max.) ? military: 25/35/55/100ns (max.) low-power operation ? idt7132/42sa active: 325mw (typ.) standby: 5mw (typ.) ? idt7132/42la active: 325mw (typ.) standby: 1mw (typ.) notes: 1. idt7132 (master): busy is open drain output and requires pullup resistor of 270 ? . idt7142 (slave): busy is input. 2. open drain output: requires pullup resistor of 270 ? . master idt7132 easily expands data bus width to 16-or-more bits using slave idt7142 on-chip port arbitration logic (idt7132 only) busy output flag on idt7132; busy input on idt7142 battery backup operation ?2v data retention (la only) ttl-compatible, single 5v 10% power supply available in 48-pin dip, lcc and flatpack, and 52-pin plcc packages military product compliant to mil-prf-38535 qml industrial temperature range (?40c to +85c) is available for selected speeds oe l ce l r/w l i/o ol- i/o 7l busy l (1,2) a 10l a 0l ce l oe l r/ w l ce r oe r r/ w r oe r ce r r/ w r i/o or- i/o 7r busy r (1,2) a 10r a 0r i/o control i/o control address decoder address decoder memory array arbitration logic 2692 drw 01 m 11 11
2 idt7132sa/la and idt 7142sa/la high speed 2k x 8 dual port static ram military, industrial and commercial temperature ranges pin configurations (1,2,3) notes: 1. all v cc pins must be connected to the power supply. 2. all gnd pins must be connected to the ground supply. 3. p48-1 package body is approximately .55 in x 2.43 in x .18 in. c48-2 package body is approximately .62 in x 2.43 in x .15 in. l48-1 package body is approximately .57 in x .57 in x .68 in. f48-1 package body is approximately .75 in x .75 in x .11 in. 4. this package code is used to reference the package diagram. 5. this text does not indicate orientation of the actual part-marking. description the idt7132/idt7142 are high-speed 2k x 8 dual-port static rams. the idt7132 is designed to be used as a stand-alone 8-bit dual-port ram or as a ?master? dual-port ram together with the idt7142 ?slave? dual-port in 16-bit-or-more word width systems. using the idt master/ slave dual-port ram approach in 16-or-more-bit memory system applications results in full-speed, error-free operation without the need for additional discrete logic. both devices provide two independent ports with separate control, address, and l/o pins that permit independent, asynchronous access for reads or writes to any location in memory. an automatic power down feature, controlled by ce permits the on-chip circuitry of each port to enter a very low standby power mode. fabricated using idt?s cmos high-performance technology, these devices typically operate on only 325mw of power. low-power (la) versions offer battery backup data retention capability, with each dual- port typically consuming 200w from a 2v battery. the idt7132/7142 devices are packaged in a 48-pin sidebraze or plastic dips, 48-pin lccs, 52-pin plccs, and 48-lead flatpacks. military grade product is manufactured in compliance with the latest revision of mil-prf-38535 qml, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 148 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 idt7132/ 7142 porc p48-1 (4) & c48-2 (4) 48-pin dip top view (5) 2692 drw 02 gnd i/o 6r i/o 5r i/o 4r i/o 3r i/o 2r i/o 1r i/o 0r i/o 7l i/o 6l i/o 5l i/o 4l ce r ce l oe l a 0l busy l r/ w l r/ w r busy r v cc oe r a 0r a 1r a 2r a 3r a 4r a 5r a 6r a 7r a 8r a 9r i/o 7r i/o 3l a 1l a 2l a 3l a 4l a 5l a 6l a 7l a 8l a 9l i/o 0l i/o 1l i/o 2l a 10l a 10r , idt7132/42l48 or f l48-1 (4) & f48-1 (4) 48-pin lcc/ flatpack top view (5) index 65 432 1 48 47 46 45 44 43 19 20 21 22 23 25 26 27 28 29 30 24 42 41 40 39 38 37 36 35 34 33 32 31 7 8 9 10 11 12 13 14 15 16 17 18 2692 drw 03 g n d c e r c e l o e l a 0 l o e r a 0r a 1r a 2r a 3r a 4r a 5r a 6r a 7r a 8r a 9r i/o 7r i / o 3 l a 1l a 2l a 3l a 4l a 5l a 6l a 7l a 8l a 9l i/o 0l i/o 1l i/o 2l b u s y l r / w l r / w r b u s y r v c c i/o 6r i / o 5 r i / o 4 r i / o 3 r i / o 2 r i / o 1 r i / o 0 r i / o 7 l i / o 6 l i / o 5 l i / o 4 l a 1 0 l a 1 0 r , capacitance (1) (t a = +25c,f = 1.0mhz) notes: 1. this parameter is determined by device characterization but is not production tested. 2. 3dv represents the interpolated capacitance when the input and output signals switch from 3v to 0v. symbol parameter conditions (2 ) max. unit c in input cap acitance v in = 3dv 11 pf c out output capacitance v out = 3dv 11 pf 2692 tbl 00
6.42 idt7132sa/la and idt 7142sa/la high speed 2k x 8 dual port static ram military, industrial and commercial temperature ranges 3 idt7132/42j j52-1 (4) 52-pin plcc top view (5) index n / c g n d oe r a 0r a 1r a 2r a 3r a 4r a 5r a 6r a 7r a 8r a 9r n/c i/o 7r 46 45 44 43 42 41 40 39 38 37 36 35 34 i/o 3l a 1l a 2l a 3l a 4l a 5l a 6l a 7l a 8l a 9l i/o 0l i/o 1l i/o 2l 8 9 10 11 12 13 14 15 16 17 18 19 20 47 48 49 50 51 52 1 2 3 4 5 6 7 33 32 31 30 29 28 27 26 25 24 23 22 21 2692 drw 04 a 1 0 l v c c a 1 0 r i / o 6 r a 0 l o e l n / c c e l c e r n / c b u s y l r / w l r / w r b u s y r i / o 5 r i / o 4 r i / o 3 r i / o 2 r i / o 1 r i / o 0 r i / o 7 l i / o 6 l i / o 5 l i / o 4 l absolute maximum ratings (1) recommended dc operating conditions recommended operating temperature and supply voltage (1,2) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v term must not exceed vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20ma for the period of v term > vcc + 10%. notes: 1. this is the parameter t a . this is the "instant on" case temperature. 2. industrial temperature: for specific speeds, packages and powers contact your sales office. notes: 1. v il (min.) = -1.5v for pulse width less than 10ns. 2. v term must not exceed vcc + 10%. notes: 1. all v cc pins must be connected to the power supply. 2. all gnd pins must be connected to the ground supply. 3. package body is approximately .75 in x .75 in x .17 in. 4. this package code is used to reference the package diagram. 5. this text does not indicate orientation of the actual part-marking. pin configurations (1,2,3) (con't.) symbol rating commercial & industrial military unit v term (2) terminal voltage with respect to gnd -0.5 to +7.0 -0.5 to +7.0 v t bias temperature under bias -55 to +125 -65 to +135 o c t stg storage temperature -65 to +150 -65 to +150 o c i out dc output current 50 50 ma 2692 tbl 01 grade ambient temperature gnd vcc military -55 o c to+125 o c0v5.0v + 10% commercial 0 o c to +70 o c0v5.0v + 10% industrial -40 o c to +85 o c0v5.0v + 10% 2692 tbl 02 symbol parameter min. typ. max. unit v cc supply voltage 4.5 5.0 5.5 v gnd ground 0 0 0 v v ih input high voltage 2.2 ____ 6.0 (2 ) v v il input low voltage -0.5 (1 ) ____ 0.8 v 2692 tbl 03
4 idt7132sa/la and idt 7142sa/la high speed 2k x 8 dual port static ram military, industrial and commercial temperature ranges dc electrical characteristics over the operating temperature and supply voltage range (1,5,8) (v cc = 5.0v 10%) notes: 1. 'x' in part numbers indicates power rating (sa or la). 2. plcc package only 3. at f = f max , address and control lines (except output enable) are cycling at the maximum frequency read cycle of 1/t rc , and using ?ac test conditions? of input levels of gnd to 3v. 4. f = 0 means no address or control lines change. applies only to inputs at cmos level standby. 5. vcc = 5v, t a =+25c for typ and is not production tested. vcc dc = 100ma (typ) 6. port "a" may be either left or right port. port "b" is opposite from port "a". 7. not available in dip packages. 8. industrial temperature: for specific speeds, packages and powers contact your sales office. 7132x20 (2) 7142x20 (2) com'l only 7132x25 (7) 7142x25 (7) com'l, ind & military 7132x35 7142x35 com'l & military symbol parameter test condition version typ. max. typ. max. typ. max. unit i cc dynamic operating current (both ports active) ce l = ce r = v il , outputs disabled f = f max (3) com'l sa la 110 110 250 200 110 110 220 170 80 80 165 120 ma mil & ind sa la ____ ____ ____ ____ 110 110 280 220 80 80 230 170 i sb1 standby current (both ports - ttl level inputs) ce l = ce r = v ih , f = f max (3) com'l sa la 30 30 65 45 30 30 65 45 25 25 65 45 ma mil & ind sa la ____ ____ ____ ____ 30 30 80 60 25 25 80 60 i sb2 standby current (one port - ttl level inputs) ce "a" = v il and ce "b" = v ih (6) active port outputs disabled f=f max (3) com'l sa la 65 65 165 125 65 65 150 115 50 50 125 90 ma mil & ind sa la ____ ____ ____ ____ 65 65 160 125 50 50 150 115 i sb3 full standby current (both ports - all cmos le ve l inp uts) ce l and ce r > v cc -0.2v v in > v cc -0.2v or v in < 0.2v, f = 0 (4) com'l sa la 1.0 0.2 15 5 1.0 0.2 15 5 1.0 0.2 15 4 ma mil & ind sa la ____ ____ ____ ____ 1.0 0.2 30 10 1.0 0.2 30 10 i sb4 full standby current (one port - all cmos le ve l inp uts) ce "a" < 0.2v and ce "b" > v cc -0.2v (6) v in > v cc - 0.2v or v in < 0.2v active port outputs disabled f = f max (3) com'l sa la 60 60 155 115 60 60 145 105 45 45 110 85 ma mil & ind sa la ____ ____ ____ ____ 60 60 155 115 45 45 145 105 2692 tbl 04a 7132x55 7142x55 com'l & military 7132x100 7142x100 com'l & military symbol parameter test condition version typ. max. typ. max. unit i cc dynamic operating current (both ports active) ce l = ce r = v il , outputs disabled f = f max (3 ) com'l sa la 65 65 155 110 65 65 155 110 ma mil & ind sa la 65 65 190 140 65 65 190 140 i sb1 standby current (both ports - ttl level inputs) ce l = ce r = v ih , f = f max (3 ) com'l sa la 20 20 65 35 20 20 55 35 ma mil & ind sa la 20 20 65 45 20 20 65 45 i sb2 standby current (one port - ttl level inputs) ce "a" = v il and ce "b" = v ih (6) active port outputs disabled f=f max (3) com'l sa la 40 40 110 75 40 40 110 75 ma mil & ind sa la 40 40 125 90 40 40 125 90 i sb3 full standby current (both ports - all cmos level inputs) ce l and ce r > v cc -0.2v v in > v cc -0.2v or v in < 0.2v, f = 0 (4) com'l sa la 1.0 0.2 15 4 1.0 0.2 15 4 ma mil & ind sa la 1.0 0.2 30 10 1.0 0.2 30 10 i sb4 full standby current (one port - all cmos level inputs) ce "a" < 0.2v and ce "b" > v cc -0.2v (6 ) v in > v cc - 0.2v or v in < 0.2v active port outputs disabled f = f max (3 ) com'l sa la 40 40 100 70 40 40 95 70 ma mil & ind sa la 40 40 110 85 40 40 110 80 2692 tbl 04b
6.42 idt7132sa/la and idt 7142sa/la high speed 2k x 8 dual port static ram military, industrial and commercial temperature ranges 5 data retention characteristics (la version only) notes: 1. v cc = 2v, t a = +25c, and is not production tested. 2. t rc = read cycle time 3. this parameter is guaranteed but not production tested. note: 1. at vcc < 2.0v leakages are undefined. dc electrical characteristics over the operating temperature supply voltage range (v cc = 5.0v 10%) data retention waveform v cc ce 4.5v 4.5v data retention mode t cdr t r v ih v ih v dr v dr 2.0v 2692 drw 05 , symbol parameter test conditions 7132sa 7142sa 7132la 7142la unit min. max. min. max. |i li | input leakage current (1) v cc = 5.5v, v in = 0v to v cc ___ 10 ___ 5a |i lo | output leakage current v cc = 5.5v, ce = v ih , v out = 0v to v cc ___ 10 ___ 5 a v ol output low voltage i ol = 4ma ___ 0.4 ___ 0.4 v v ol open drain output low voltage ( busy ) i ol = 16ma ___ 0.5 ___ 0.5 v v oh output high voltage i oh = -4ma 2.4 ___ 2.4 ___ v 2692 tbl 05 symbol parameter test condition min. typ. (1 ) max. unit v dr v cc for data retention v cc = 2.0v 2.0 ___ ___ v i ccdr data retention current ce > v cc -0.2v v in > v cc -0.2v or mil. & ind. ___ 100 4000 a com'l. ___ 100 1500 a t cd r (3 ) chip deselect to data retention time v in < 0.2v 0 ___ ___ ns t r (3 ) operation recovery time t rc (2 ) ___ ___ ns 2692 tb l 0 6
6 idt7132sa/la and idt 7142sa/la high speed 2k x 8 dual port static ram military, industrial and commercial temperature ranges 5v 1250 ? 30pf* 775 ? data out 5v 1250 ? 775 ? 5pf* data out 2692 drw 06 *100pf for 55 and 100ns versions 5v 270 ? 30pf* busy *100pf for 55 and 100ns versions , figure 2. output test load (for t hz , t lz , t wz , and t ow ) * including scope and jig figure 1. ac output test load figure 3. busy ac output test load ac test conditions input pulse lev els input ris e/fall time s input timing re fe rence lev els output reference levels output load gnd to 3.0v 3ns max. 1.5v 1.5v figures 1, 2, and 3 2692 tbl 07
6.42 idt7132sa/la and idt 7142sa/la high speed 2k x 8 dual port static ram military, industrial and commercial temperature ranges 7 ac electrical characteristics over the operating temperature and supply voltage range (3,5) notes: 1. transition is measured 0mv from low or high-impedance voltage output test load (figure 2). 2. plcc package only. 3. 'x' in part numbers indicates power rating (sa or la). 4. this parameter is guaranteed by device characterization, but is not production tested. 5. industrial temperature: for specific speeds, packages and powers contact your sales office. 7132x20 (2) 7142x20 (2) com'l only 7132x25 (2) 7142x25 (2) com'l, ind & military 7132x35 7142x35 com'l & military unit symbol parameter min.max.min.max.min.max. read cycle t rc read cycle time 20 ____ 25 ____ 35 ____ ns t aa address access time ____ 20 ____ 25 ____ 35 ns t ace chip enable access time ____ 20 ____ 25 ____ 35 ns t aoe output enable access time ____ 11 ____ 12 ____ 20 ns t oh output hold from address change 3 ____ 3 ____ 3 ____ ns t lz outp ut lo w-z time (1,4) 0 ____ 0 ____ 0 ____ ns t hz output high-z time (1,4) ____ 10 ____ 10 ____ 15 ns t pu chip enable to power up time (4) 0 ____ 0 ____ 0 ____ ns t pd chip disable to power down time (4) ____ 20 ____ 25 ____ 35 ns 2692 tbl 08a 7132x55 7142x55 com'l & military 7132x100 7142x100 com'l & military unit symbol parameter min. max. min. max. read cycle t rc read cycle time 55 ____ 100 ____ ns t aa address access time ____ 55 ____ 100 ns t ace chip enable access time ____ 55 ____ 100 ns t aoe output enable access time ____ 25 ____ 40 ns t oh output hold from address change 3 ____ 10 ____ ns t lz output low-z time (1,4) 5 ____ 5 ____ ns t hz output high-z time (1,4) ____ 25 ____ 40 ns t pu chip enable to power up time (4) 0 ____ 0 ____ ns t pd chip disable to power down time (4 ) ____ 50 ____ 50 ns 2692 tbl 08b
8 idt7132sa/la and idt 7142sa/la high speed 2k x 8 dual port static ram military, industrial and commercial temperature ranges timing waveform of read cycle no. 2, either side (1) notes: 1. r/ w = v ih, ce = v il, and is oe = v il. address is valid prior to the coincidental with ce transition low. 2. t bdd delay is required only in the case where the opposite port is completing a write operation to the same address location. for si multaneous read operations, busy has no relationship to valid output data. 3. start of valid data depends on which timing becomes effective last t aoe , t ace , t aa , and t bdd . 4. timing depends on which signal is asserted last, oe or ce . 5. timing depends on which signal is de-asserted first, oe or ce . timing waveform of read cycle no. 1, either side (1) address data out t rc t oh previous data valid t aa t oh data valid 2692 drw 07 t bddh (2,3) busy out ce t hz (5) t lz (4) t pd (3) valid data t pu 50% oe data out current i cc i ss 50% 2692 drw 08 t lz (4) t hz (5) t ace t aoe (3)
6.42 idt7132sa/la and idt 7142sa/la high speed 2k x 8 dual port static ram military, industrial and commercial temperature ranges 9 ac electrical characteristics over the operating temperature supply voltage range (5,6) notes: 1. transition is measured 0mv from low or high-impedance voltage with output test load (figure 2). this parameter is guaranteed by device characterization but is not production tested. 2. plcc package only. 3. for master/slave combination, t wc = t baa + t wp , since r/w = v il must occur after t baa . 4. if oe is low during a r/ w controlled write cycle, the write pulse width must be the larger of t wp or (t wz + t dw ) to allow the i/o drivers to turn off data to be placed on the bus for the required t dw . if oe is high during a r/ w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wp . 5. 'x' in part numbers indicates power rating (sa or la). 6. industrial temperature: for specific speeds, packages and powers contact your sales office. symbol parameter 7132x20 (2) 7142x20 (2) com'l only 7132x25 (2) 7142x25 (2) com'l, ind & military 7132x35 7142x35 com'l & military unit min. max. min. max. min. max. wri te cycle t wc write cycle time (3) 20 ____ 25 ____ 35 ____ ns t ew chip enable to end-of-write 15 ____ 20 ____ 30 ____ ns t aw address valid to end-of-write 15 ____ 20 ____ 30 ____ ns t as address set-up time 0 ____ 0 ____ 0 ____ ns t wp write pulse width (4) 15 ____ 15 ____ 25 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ ns t dw data valid to end-of-write 10 ____ 12 ____ 15 ____ ns t hz output high-z time (1) ____ 10 ____ 10 ____ 15 ns t dh data hold time 0 ____ 0 ____ 0 ____ ns t wz write enable to output in high-z (1) ____ 10 ____ 10 ____ 15 ns t ow output active from end-of-write (1) 0 ____ 0 ____ 0 ____ ns 2692 tbl 09 symbol parameter 7132x55 7142x55 com'l & military 7132x100 7142x100 com'l & military unit min. max. min. max. write cycle t wc write cycle time (3 ) 55 ____ 100 ____ ns t ew chip enable to end-of-write 40 ____ 90 ____ ns t aw address valid to end-of-write 40 ____ 90 ____ ns t as address set-up time 0 ____ 0 ____ ns t wp write pulse width (4) 30 ____ 55 ____ ns t wr write recovery time 0 ____ 0 ____ ns t dw data valid to end -of-write 20 ____ 40 ____ ns t hz output high-z time (1 ) ____ 25 ____ 40 ns t dh data hold time 0 ____ 0 ____ ns t wz write enable to outp ut in high-z (1) ____ 30 ____ 40 ns t ow output active from end-of-write (1) 0 ____ 0 ____ ns 2692 tbl 10
10 idt7132sa/la and idt 7142sa/la high speed 2k x 8 dual port static ram military, industrial and commercial temperature ranges t wc address ce r/ w data in t as (6) t ew (2) t wr (3) t dw t dh t aw 2692 drw 10 timing waveform of write cycle no. 1, (r/ w controlled timing) (1,5,8) timing waveform of write cycle no. 2, ( ce controlled timing) (1,5) notes: 1. r/ w or ce must be high during all address transitions. 2. a write occurs during the overlap (t ew or t wp ) of ce = v il and r/ w = v il . 3. t wr is measured from the earlier of ce or r/ w going high to the end of the write cycle. 4. during this period, the l/o pins are in the output state and input signals must not be applied. 5. if the ce low transition occurs simultaneously with or after the r/ w low transition, the outputs remain in the high-impedance state. 6. timing depends on which enable signal (ce or r/w) is asserted last. 7. this parameter is determined be device characterization, but is not production tested. transition is measured 0mv from steady state with the output test load (figure 2). 8. if oe is low during a r/ w controlled write cycle, the write pulse width must be the larger of t wp or (t wz + t dw ) to allow the i/o drivers to turn off data to be placed on the bus for the required t dw . if oe is high during a r/ w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wp . t wc address oe ce r/ w data out data in t as (6) t ow t dw t dh t aw t wp (2) t hz (7) (4) (4) t wz (7) t hz (7) 2692 drw 09 t wr (3)
6.42 idt7132sa/la and idt 7142sa/la high speed 2k x 8 dual port static ram military, industrial and commercial temperature ranges 11 ac electrical characteristics over the operating temperature and supply voltage range (7,8) notes: 1. plcc package only. 2. port-to-port delay through ram cells from the writing port to the reading port, refer to ?timing waveform of write with port -to-port read and busy.? 3. to ensure that the earlier of the two ports wins. 4. t bdd is a calculated parameter and is the greater of 0, t wdd ? t wp (actual) or t ddd ? t dw (actual). 5. to ensure that a write cycle is inhibited on port "b" during contention on port "a". 6. to ensure that a write cycle is completed on port "b" after contention on port "a". 7. 'x' in part numbers indicates power rating (sa or la). 8. industrial temperature: for specific speeds, packages and powers contact your sales office. 7132x20 (1) 7142x20 (1) com'l only 7132x25 (2) 7142x25 (2) com'l, ind & military 7132x35 7142x35 com'l & military symbol parameter min.max.min.max.min.max.unit busy timing (for master idt7132 only) t baa busy access time from address ____ 20 ____ 20 ____ 20 ns t bda busy disable time from address ____ 20 ____ 20 ____ 20 ns t bac busy access time from chip enable ____ 20 ____ 20 ____ 20 ns t bdc busy disable time from chip enable ____ 20 ____ 20 ____ 20 ns t wdd write pulse to data delay (2) ____ 50 ____ 50 ____ 60 ns t wh write hold after busy (6) 12 ____ 15 ____ 20 ____ ns t ddd write data valid to read data delay (2) ____ 35 ____ 35 ____ 35 ns t aps arbitratio n priority set-up time (3) 5 ____ 5 ____ 5 ____ ns t bdd busy disable to valid data (4) ____ 25 ____ 35 ____ 35 ns busy timing (for slave idt7142 only) t wb write to busy input (5) 0 ____ 0 ____ 0 ____ ns t wh write hold after busy (6) 12 ____ 15 ____ 20 ____ ns t wdd write pulse to data delay (2) ____ 40 ____ 50 ____ 60 ns t ddd write data valid to read data delay (2) ____ 30 ____ 35 ____ 35 ns 2692 tbl 11a 7132x55 7142x55 com'l & military 7132x100 7142x100 com'l & military symbol parameter min. max. min. max. unit busy timing (for master idt7132 only) t baa busy access time from address ____ 30 ____ 50 ns t bda busy disable time from address ____ 30 ____ 50 ns t bac busy access time from chip enable ____ 30 ____ 50 ns t bdc busy disable time from chip enable ____ 30 ____ 50 ns t wdd write pulse to data delay (2) ____ 80 ____ 120 ns t wh write hold after busy (6) 20 ____ 20 ____ ns t ddd write data valid to read data delay (2) ____ 55 ____ 100 ns t aps arbitration priority set-up time (3) 5 ____ 5 ____ ns t bdd busy disable to valid data (4) ____ 50 ____ 65 ns busy timing (for slave idt7142 only) t wb write to busy inp ut (5) 0 ____ 0 ____ ns t wh write hold after busy (6) 20 ____ 20 ____ ns t wdd write pulse to data delay (2) ____ 80 ____ 120 ns t ddd write data valid to read data delay (2) ____ 55 ____ 100 ns 2692 tbl 11b
12 idt7132sa/la and idt 7142sa/la high speed 2k x 8 dual port static ram military, industrial and commercial temperature ranges timing waveform of write with busy (4) notes: 1. t wh must be met for both busy input (idt7142, slave) or output (idt7132, master). 2. busy is asserted on port "b" blocking r/ w "b" , until busy "b" goes high. 3. t wb applies only to the slave version (idt7142). 4. all timing is the same for the left and right ports. port 'a' may be either the left or right port. port "b" is opposite from port "a". timing waveform of write with port-to-port read and busy (2,3,4) busy "b" 2692 drw 12 r/ w "a" t wp t wh (1) t wb r/ w "b" (2) (3) , t wc t wp t dw t dh t bdd t ddd t bda t wdd addr "b" data out"b" data in"a" addr "a" match valid match valid r/ w "a" busy "b" t aps (1) 2692 drw 11 t baa notes: 1. to ensure that the earlier of the two ports wins. t aps is ignored for slave (idt7142). 2. ce l = ce r = v il 3. oe = v il for the reading port. 4. all timing is the same for the left and right ports. port "a" may be either the left or right port. port "b" is opposite from port "a".
6.42 idt7132sa/la and idt 7142sa/la high speed 2k x 8 dual port static ram military, industrial and commercial temperature ranges 13 timing waveform of busy arbitration controlled by ce timing (1) timing waveform of busy arbitration controlled by address match timing (1) truth tables table i. non-contention read/write control (4) notes: 1. a 0l - a 10l a 0r - a 10r 2. if busy = l, data is not written. 3. if busy = l, data may not be valid, see t wdd and t ddd timing. 4. 'h' = v ih , 'l' = v il , 'x' = don?t care, 'z' = high impedance t aps (2) addr "a" and "b" addresses match t bac t bdc ce "b" ce "a" busy "a" 2692 drw 13 busy "b" addresses do not match addresses match t aps (2) addr "a" addr "b" 2692 drw 14 t baa t bda t rc or t wc notes: 1. all timing is the same for left and right ports. port ?a? may be either left or right port. port ?b? is the opposite from por t ?a?. 2. if t aps is not satisified, the busy will be asserted on one side or the other, but there is no guarantee on which side busy will be asserted (7132 only). left or right port (1 ) r/ w ce oe d 0-7 function x h x z port disabled and in power-down mode, i sb2 or i sb4 xhx z ce r = ce l = v ih , power-down mode, i sb1 or i sb3 llx data in data on port written into memory (2 ) hl ldata out data in memory output on port (3 ) x l h z high impedance outputs 2692 tbl 12
14 idt7132sa/la and idt 7142sa/la high speed 2k x 8 dual port static ram military, industrial and commercial temperature ranges the busy outputs on the idt7132 ram master are totem-pole type outputs and do not require pull-up resistors to operate. if these rams are being expanded in depth, then the busy indication for the resulting array does not require the use of an external and gate. width expansion with busy logic master/slave arrays when expanding an sram array in width while using busy logic, one master part is used to decide which side of the sram array will receive a busy indication, and to output that indication. any number of slaves to be addressed in the same address range as the master, use the busy signal as a write inhibit signal. thus on the idt7132/ idt7142 srams the busy pin is an output if the part is master (idt7132), and the busy pin is an input if the part is a slave (idt7142) as shown in figure 3. if two or more master parts were used when expanding in width, a split decision could result with one master indicating busy on one side of the array and another master indicating busy on one other side of the array. this would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. the busy arbitration, on a master, is based on the chip enable and address signals only. it ignores whether an access is a read or write. in a master/slave array, both address and chip enable must be valid long enough for a busy flag to be output from the master before the actual write pulse can be initiated with either the r/ w signal or the byte enables. failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. table ii ? address busy arbitration notes: 1. pins busy l and busy r are both outputs for idt7132 (master). both are inputs for idt7142 (slave). busy x outputs on the idt7132 are open drain, not push-pull outputs. on slaves the busy x input internally inhibits writes. 2. 'l' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'h' if the inputs to the opposite port became stable after the address and enable inputs of this port. if t aps is not met, either busy l or busy r = low will result. busy l and busy r outputs can not be low simultaneously. 3. writes to the left port are internally ignored when busy l outputs are driving low regardless of actual logic level on the pin. writes to the right port are internally ignored when busy r outputs are driving low regardless of actual logic level on the pin. functional description the idt7132/idt7142 provides two ports with separate control, address and i/o pins that permit independent access for reads or writes to any location in memory. the idt7132/idt7142 has an automatic power down feature controlled by ce . the ce controls on- chip power down circuitry that permits the respective port to go into a standby mode when not selected ( ce = v ih ). when a port is enabled, access to the entire memory array is permitted. busy logic busy logic provides a hardware indication that both ports of the ram have accessed the same location at the same time. it also allows one of the two accesses to proceed and signals the other side that the ram is ?busy?. the busy pin can then be used to stall the access until the operation on the other side is completed. if a write operation has been attempted from the side that receives a busy indication, the write signal is gated internally to prevent the write from proceeding. the use of busy logic is not required or desirable for all applica- tions. in some cases it may be useful to logically or the busy outputs together and use any busy indication as an interrupt source to flag the event of an illegal or illogical operation. figure 4. busy and chip enable routing for both width and depth expansion with idt7132 (master) and (slave) idt7142 srams. 2692 drw 15 master dual port sram busy l busy r ce master dual port sram busy l busy r ce slave dual port sram busy l busy r ce slave dual port sram busy l busy r ce busy l busy r d e c o d e r 5v 5v 270 ? 270 ? inputs outputs function ce l ce r a ol -a 10l a or -a 10r busy l (1 ) busy r (1) xxno match h h normal h x match h h normal x h match h h normal l l match (2) (2) write inhibit (3) 2692 tbl 13
6.42 idt7132sa/la and idt 7142sa/la high speed 2k x 8 dual port static ram military, industrial and commercial temperature ranges 15 ordering information idt xxxx a 999 a a device type power speed package process/ temperature range blank i (1) b commercial (0 cto+70 c) industrial (-40 cto+85 c) military (-55 cto+125 c) compliant to mil-prf-38535 qml p c j l48 f 48-pin plastic dip (p48-1) 48-pin sidebraze dip (c48-2) 52-pin plcc (j52-1) 48-pin lcc (l48-1) 48-pin ceramic flatpack (f48-1) 20 25 35 55 100 commercial plcc only commercial, industrial & military commercial & military commercial & military commercial & military ? ? ? la sa low power standard power 7132 7142 16k (2k x 8-bit) master dual-port ram 16k (2k x 8-bit) slave dual-port ram speed in nanoseconds 2692 drw 16 , note: 1. industrial temperature range is available. for specific speeds, packages and powers contact your sales office. datasheet document history 03/24/99: initiated datasheet document history converted to new format cosmetic and typographical corrections pages 2 and 3 added additional notes to pin configurations 06/08/99: changed drawing format 08/26/99: page 14 changed busy logic and width expansion copy 11/10/99: replace d idt logo 01/12/00: pages 1 and 2 moved full "description" to page 2 and adjusted page layouts page 1 added "(laonly)" to paragraph page 2 fixed p48-1 body package description page 3 increased storage temperature parameters clarified t a parameter page 4 dc electrical parameters?changed wording from "open" to "disabled" page 6 added asteriks to figures 1 and 3 in drw 06 page 14 corrected part numbers changed 500mv to 0mv in notes datasheet document history continued on page 16
16 idt7132sa/la and idt 7142sa/la high speed 2k x 8 dual port static ram military, industrial and commercial temperature ranges datasheet document history (cont'd) 06/11/04: page 6 corrected errors in figure 3 by changing 1250 ? to 270 ? and removing "or int" and int page 4, 7, 9, 11 & 15 clarified industrial temp offering for 25ns page 5 removed int from v ol parameter in dc electrical characteristics table page 6 updated ac test conditions input rise/fall times from 5ns to 3ns corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-5166 831-754-4613 santa clara, ca 95054 fax: 408-492-8674 dualporthelp@idt.com www.idt.com the idt logo is a registered trademark of integrated device technology, inc.

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